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My research is to implement hardware oriented neural network algorithm for efficient FPGA implementation. Neural network has outstanding performance in various fields such as automation, robotics and so on. Deep Neural Network can be applied for only inference mode or trainable mode. In inference mode, the DNN uses the pre-trained model and does not update with the changing in time and environment, where in trainable mode, the weights of the model update corresponding to the changes, allow the network to learn. To apply DNN, the processing system can be categorized into three major class, which are software system (CPU, GPU, etc.), hardware system (FPGA, ASIC, etc.) and software-hardware combination system (SoC, etc.)
However, training neural network on device is relatively difficult due to the high computation cost. FPGA is an electronic hardware device that enable real time processing with very low power consumption. Thus it is suitable for application of mobile device and embedded system. However, the implementation of neural network into FPGA is difficult because the difference in architecture resulting common algorithm unable to apply in it efficiently, in term of either resources or performance as well. Moreover, the constraint of resources in FPGA resulting the higher priority in efficiently utilize the resource optimally.
The biggest problem of implement DNN in embedded system is the high power consumption caused by the complex computation. This problem can be tackled by implement with FPGA, which provides real-time processing with low power consumption due to its parallel processing characteristic. However, the current algorithms of neural network are usually developed in CPU or GPU, which is software-based and is not suitable for FPGA. The hardware oriented algorithms are required.
In this research, we focus on dropout algorithm and propose an alternative dropout algorithm which is hardware-oriented, by eliminating the required of random number generator, and enable in parallel processing, resulting real-time processing and resource-saving. The dropout technique is usually applied in training the DNN for avoiding overfitting problem, which is caused by over-train the model and resulting drops in performance.
The experiment had been carried out by separating into two part: software verification and hardware synthesis comparison. In software verification part, various architecture of neural network such as Multi-Layer Perceptron (MLP) and Convolutional Neural Network (CNN) had been trained with different type of dataset (MNIST, CIFAR-10 and etc.) respectively. Experiments were carried out with training the neural networks without dropout algorithm, with conventional dropout, and with the proposed method. Where in the comparison of hardware synthesis, 3 approaches had been carried out to compare the resources consumption and the processing speed (clock cycle). The 3 approaches which are including the conventional dropout in series processing, conventional dropout in parallel processing, and the proposed method.
In this research, several results can be observed and verified through the experiment.
– The proposed method achieved the same effect to the conventional dropout algorithm which can solved the overfitting problem. (Compare in aspect of recognition accuracy)
– The proposed method able to process in parallel, which allow the process complete in a single clock cycle (where the processing speed depend to the frequency of clock)
– The resource consumption is the least compare among the 3 approaches, which is the most efficient in implementation into FPGA.